1. Technical Field of the Invention
The present invention relates to intra-chip data communication techniques for integrated circuit devices and, in particular, to a data transfer architecture useful for handling data communications between the computational blocks present within a system on chip (SoC) type integrated circuit device.
2. Description of Related Art
Advances in semiconductor technology allow complex systems composed of a plurality of computational blocks to be implemented on a single integrated circuit (IC) chip. Such devices are often referred to as system on chip (SoC) devices. Within such devices, it is critical to enable the transfer of data among and between the included computational blocks. However, the infrastructure which supports such intra-chip data transfers often becomes a bottleneck for speed performance with respect to the SoC device.
A prior art approach utilizes a global bus architecture for transferring data from a source computational block to a destination computational block. The global bus architecture solution, however, does not scale well as the number of blocks and the area of the SoC increases.
Although there are a number of different types of known global bus architectures, the concept of a global bus architecture solution can be simplified into a basic architecture. By considering this simplification, the limitations imposed by the global bus architecture solution can be evaluated.
Reference is now made to FIG. 1 wherein there is shown a block diagram of a basic global bus architecture 10. The bus architecture 10 may be used within an SoC device for purposes of interconnecting a plurality of computational blocks (not explicitly illustrated, see FIG. 2). Each computational block may act as a data initiator (i.e., a sender or transmitter), a data target (i.e., an acceptor or receiver), or both. To accomplish a communication as a data initiator, each computational block can access the bus architecture 10 through an initiator port 12 (n such ports being shown in FIG. 1). To accomplish a communication as a data target, each computational block can access the bus architecture 10 through a target port 14 (n such ports being shown in FIG. 1). The configuration of bus architecture 10 can thus support communications among and between n computational block (see, FIG. 2).
The bus architecture 10 includes an arbitration unit 16 and a data steering unit 18. The data steering unit 18 operates to control the flow of data from the data initiator (more specifically, the particular initiator port 12) to the data target (more specifically, the particular target port 14). In the bus architecture 10, the data steering unit 18 supports the connection of any initiator port 12 to any target port 14. The establishment of such connections is controlled by the arbitration unit 16 which assigns available communication resources within the data steering unit 18 to support a data transmission. More specifically, the arbitration unit 16 determines what access a certain initiator (from an initiator port 12) is to be given to a certain target (at a target port 14). The access determination decision is made by the arbitration unit 16 based on the availability of the target and the priority of the initiator. For example, the arbitration unit 16 may first determine whether the target is ready to receive the data communication (for example, is it available). Next, if more than one initiator has a need to make a data transfer to the ready and available target, the arbitration unit 16 determines which initiator port (or more specifically, which computational block) has a highest communications priority level. The initiator having the highest relative priority is then granted access through the bus architecture to communicate (through the date steering unit 18) with the target. This method of access arbitration requires the arbitration unit 16 to keep track of the availability status and relative priorities of all the computational blocks (targets and initiators) in the system. For an n x n system (i.e., one with n initiator ports and n target ports), the complexity of the arbitration unit 16 accordingly scales with n.
The data steering unit 18 controls the flow of data from initiator to target. Following the arbitration unit 16 granting an initiator (port) access to a specific target (port), the data steering unit 18 operates to transfer the data. The data steering unit 18 is configured in a bus format having communications resources which are allocated by the arbitration unit 16. Since any initiator (port) can connect to any target (port), for example through the use of an n plurality of n:1 multiplexers, the complexity of the data steering unit 18 also scales with n.
The scaling with n characterization of the both the arbitration unit 16 and data steering unit 18 is especially troublesome as the number of computational blocks increases with increased complexity of the SoC device design. Increases in n expose the weaknesses of the conventional bus architecture 10 solution.
The speed performance of the bus architecture 10 can be quantified in terms of data throughput (which is the reciprocal of the delay of the arbitration/data steering units). The delay in the arbitration/data steering units is composed of two components:                a logic delay relating to the time taken by the included circuitry to perform the logic operations necessary to implement the functions performed by the arbitration and data steering units; and        an interconnect delay relating to the time taken to establish communication connections from the blocks/ports to the arbitration and data steering units.        
The logic delay of the arbitration and data steering units is a function of the number of devices, n. As the system scales, the number of logic devices needed increases and the data throughput is adversely affected by the time taken by the increased number of logic devices to perform the necessary data processing operations.
The interconnect delay is a function of the length of the wire, which is strongly affected by the physical implementation. Since the global bus architecture 10 operates on the signals from all the n blocks, it requires a physical implementation with a centralized placement of the arbitration and data steering units. The signals from all the blocks/ports are routed to this central location. This point is illustrated by FIG. 2 which shows a common floorplan for the global bus architecture utilizing centralized arbitration and data steering units. Due to the centralization requirement, as the area of the SoC increases, perhaps due to increases in the number n of included computational blocks, the interconnect length and hence the interconnect delay increases.
A need accordingly exists for an improved data communications architecture that supports the global connectivity requirements of an SoC with respect to a plurality of included computational blocks.